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document number: mc33730 rev. 9.0, 8/2012 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2009 - 2012. all rights reserved. switch mode power supply with multiple linear regulators the 33730 is a multiple output power supply integrated circuit for automotive applications. the integr ated circuit (ic) incorporates a switching regulator, which operates over a wide input voltage range from 4.5 to 26.5 v. the step-down switching regulator uses a fixed frequency pulse- width modulation (pwm) voltage mode control. it has a 3.5 a current limit (typical) and the slew-rate is adjustable via a control pin to reduce switching noise. the switching regulator has an adjustable frequency oscillator, which allows the user to optimize its operation over a wide range of input voltages and component values. the linear regulators can be configured either as two normal mode regulators (v dd3 , v ddl ) and one standby regulator (v kam ), or as one normal mode linear regulator (v ddl ) and two standby regulators (v kam and v dd3 standby). two prot ected outputs [vref (1, 2)] are used to provide power to external sensors. features ? provides all regulated voltages for freescale 32-bit microcontroller family ? adjustable frequency switching buck regulator with slew-rate control ? power sequencing provided ? programmable voltages v ddl , v dd3 - 3% accuracy ? programmable standby regulator v kam - 15% accuracy, operating down to 4.5 v at the ka_vbat pin ?v dd3 can be programmed as an optional second standby regulator with 15% accuracy ? provides two 5.0 v protected supplies for sensors ? provides reverse battery protection fet gate drive ? provides necessary mcu monitoring and fail-safe support figure 1. 33730 simplified application diagram switching power supply ek suffix (pb-free) 98arl10543d 32-lead soicw-ep 33730 ordering information device (add r2 suffix for tape and reel ) temperature range (t a ) package mcz33730ek - 40 c to 125 c 32-soicw-ep MC33730EK * * recommended device for all new designs vbat ka_vbat vign vref1,2 gnd hrt boot sw vddh vcomp vdd3_b vdd3 vddl vkam rsts + + 5.0 v + + inv vddl_b 5.0 v ka_1.0 v 1.5 v mcu (32 bit) 3.3 v 33730 p1 p2 pfd p3 regon ign_on cp 5.0v
analog integrated circuit device data 2 freescale semiconductor 33730 device variations device variations table 1. device variations part no. temperature range description mcz33730ek - 40 c to 125 c reset detect circuitry MC33730EK improved vddl and vdd3 reset detect circuitry
analog integrated circuit device data freescale semiconductor 3 33730 internal block diagram internal block diagram figure 2. 33730 simplifi ed internal block diagram 5.0 v i li m =15 0ma 26.5 v,-1v,t lim uvlo /ovlo vbat vbat ka_vbat vkam cp pfd reg on vign ign_on vref1 vref2 p1 p2 p3 rstkam rsth rst3 rstl sw sw freq boot sr inv vcomp vddh vdd3_b vdd3 vddl_b vddl hrt gnd oscillator feed forward ramp generator hs drive level shifter vkam 15 ma, i lim, t lim protection fet drive charge pump ref. voltage programming block 5.0 v i lim =150 ma 26.5 v,-1v,t lim standby control buck control logic cp + ? + ? + ? enable v kam reset detect v ddh reset detect v dd3 reset detect v ddl reset detect hr timer v kam, v ddl, v dd3, v dd3_sby reference voltage bandgap preference t-lim v bg vdd3 i lim , t lim vdd3_sby i lim , t lim vddl i lim 10.4 k 1.98 k v bg
analog integrated circuit device data 4 freescale semiconductor 33730 pin connections pin connections figure 3. 33730 pin connections table 2. 33730 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name pin function formal name definition 1 hrt analog output hardware reset timer this pin is the hardware reset timer programmed with an external resistor. 2 rstkam open drain vkam reset this pin is an open drain reset output, monitoring the v kam supply to the microprocessor. 3 rsth open drain vddh reset this pin is an open drain reset output, monitoring the v ddh regulator. 4 rstl open drain vddl reset this pin is an open drain reset output, monitoring the v ddl regulator. 5 rst3 open drain vdd3 reset this pin is an open drain reset output, monitoring the v dd3 regulator. 6 vref2 power output vref output 2 this pin is the output of the protec ted supply vref2. the pin is supplied from the v ddh through the protection fet. 7 vddl analog input vddl regulator this pin is the v ddl regulator output feedback pin. 8 vddh analog/ power input vddh regulator this pin is the 5.0 v output feedback pi n of the buck regulator. the pin is also a power input for the protected outputs vref1,2. 9 vddl_b analog output vddl regulator base drive vddl linear regulator base drive. 10 vref1 power output vref output 1 this pin is the output of the protec ted supply vref1. the pin is supplied from the v ddh through the protection fet. 11 regon logic input regulator hold on regulator hold on input pin (5.0 v logic level input). 12 ign_on open drain vign status this open drain output signals the status of the vign pin. 13 vcomp analog output compensation this pin provides switching pre-regulat or compensation, it is the output of the error amplifier. 14 inv analog input inverting input inverting input of the switching regulator error amplifier. 15 freq analog input frequency adjustment frequency adjustment of the switching regulator. the value of the resistor to ground at this pin determines the oscillator frequency. note: the exposed pad is electrically and t hermally connected to the ic ground. hrt rstkam rsth rstl rst3 vref2 vddl vddh vddl_b vref1 regon ign_on vcomp inv freq p1 p3 vign gnd vdd3_b vdd3 vkam cp ka_vbat vbat vbat sw sw sr boot pfd p2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
analog integrated circuit device data freescale semiconductor 5 33730 pin connections 16 p1 (1) logic input programming pin 1 programming pin 1 for the v dd3 , v ddl , and v kam reference voltages. 17 p2 (1) logic input programming pin 2 programming pin 2 for the v dd3 , v ddl , v kam reference voltages. 18 pfd analog output protection fet drive reverse battery protection fet gate drive. 19 boot analog input bootstrap this pin is connected to the bootstrap capacitor. 20 sr analog input slew-rate slew-rate control of the switching regulator. 21,22 sw power output switch node these pins are the source of the internal power switch (n-channel mosfet). 23,24 vbat power input battery voltage supply voltage supply to the ic (external reverse battery protection needed in some applications). 25 ka_vbat power input keep alive supply this pin is the keep alive supply input. 26 cp analog output charge pump external capacitor reservoir of the internal charge pump. 27 vkam power output keep alive memory keep-alive memory (standby) supply output. 28 vdd3 analog input v dd3 linear regulator this is a v dd3 regulator output feedback pin. this pin is also the output of the v dd3 standby regulator. 29 vdd3_b analog output vdd3 linear regulator base drive this pin can be used also as an additional standby regulator without the external pass transistor. 30 gnd ground ground this pin is a ground. 31 vign analog input voltage ignition this pin is the ignition switch contro l input pin. it contains an internal protection diode. 32 p3 (1) logic input programming pin 3 programming pin 3 for the v dd3 , v ddl , and v kam reference voltages. notes 1. programming pins must never be left fl oating, they must be tied to ground or protected battery voltage depending on the outpu t voltage selections desired. table 2. 33730 pin de finitions(continued) a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33730 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit supply voltage (vbat) v bat - 0.3 to +40 v keep-alive supply voltage (ka_vbat) ka_v bat - 18 to +40 v control inputs (v ign , p1, p2, p3), pfd output - 18 to +40 v bootstrap voltage (boot, sr) referenced to ground v boot - 0.3 to +50 v bootstrap voltage (boot, sr) referenced to sw v boot - v sw - 0.3 to +12 v charge pump output voltage (cp) v cp - 0.3 to +12 v switch node voltage sw v sw - 2.0 to +40 v sensor supplies (vref1, vref2) v ref - 1.0 to +26.5 v sensor supplies (vref1, vref2) maximum slew rate v refmaxsr 2.0 v/s regulator voltages (v ddh ,v dd3 , v dd3_b , v ddl ,v ddl_b , v kam ) v reg - 0.3 to +7.0 v open drain outputs ( rsth , rstl , rst3 , rstkam , ign_on) v dd - 0.3 to +7.0 v regon input v regon -0.3 to +7.0 v analog inputs (vcomp, inv, freq, hrt) v in - 0.3 to + 3.0 v esd voltage (2) human body model - hbm (all pins except boot, vddl, rstl) human body model - hbm (pins boot, vddl, rstl) machine model - mm (all pins) charge device model - cdm (all pins) v esd 2000 1500 200 750 v operational package temperature (ambient temperature) t a_max - 40 to + 125 c storage temperature t sto - 65 to + 150 c peak package reflow temperature during reflow (3) , (4) t pprt note 4 c maximum junction temperature t j_max 150 c thermal resistance, junction to ambient (5) r j-a 41 c/w thermal resistance, junction to case (6) r j-c 1.2 c/w notes 2. esd testing is performed in accordance with the human body m odel (hbm) (aec-q100-2), the machine model (mm) (aec-q100-003), r zap = 0 ), and the charge device model (cdm), robotic (aec-q100-011). 3. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 4. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 5. thermal resistance measured in accordance with eia/jesd51-2. 6. theoretical thermal resistance from the die junction to the exposed pad.
analog integrated circuit device data freescale semiconductor 7 33730 electrical characteristics recommended operating conditions recommended operating conditions table 4. recommended operating conditions all voltages are with respect to ground unless otherwise noted. parameter value unit supply voltages (v bat , ka_v bat ) *6.0 to 26.5 v switching regulator output current (i vddh ) total, vbat = 6.0 to 26.5 v 0 to 2.0 a v dd3 standby output current 0 to 15 ma v kam standby output current 0 to 15 ma v ref1,2 output current 0 to 100 ma switching frequency range 100 to 500 khz * tracks battery voltage from 6.0 down to 4.5 v.
analog integrated circuit device data 8 freescale semiconductor 33730 electrical characteristics static electrical characteristics static electrical characteristics table 5. static electr ical characteristic characteristics noted under conditions 6.0 v ka_v bat = v bat 26.5 v, - 40 c t a 125 c using the typical application circuit, unless otherwise noted. characteristic symbol min typ max unit general keep-alive start-up voltage (at the ka_vbat pin), vkam output up v kam_stup 4.5 ? ? v start-up voltage (at the ka_vbat pin), vdd3, vdd3 standby, vddl up v stup 4.5 ? ? v over-voltage shutdown voltage at ka_vbat pin rising v shdn_r 35 ? 42 v under-voltage lock-out voltage at ka_vbat pin falling voltage at ka_vbat pin rising under-voltage lock-out hysteresis (7) v uvlo_f v uvlo_r v uvlo_hys 3.6 3.7 ? ? ? 0.1 4.3 4.4 ? v sleep quiescent current (sleep mode) v ign = 0 v, regon = 0 v, i vkam = 0 ma, v dd3 off, v bat = 14.0 v, ka_v bat = 14 v (p1=1, p2=1, p3=1) i q ? ? 500 a switching regulator (vddh) buck converter output voltage v bat = 6.0 to 26.5 v, i load = 100 ma v bat = 26.5 to 35 v, i load = 100 ma v ddh 4.9 4.85 5.0 5.0 5.1 5.15 v switching regulator current limit ( see figure 5 ) pulse-by-pulse current limit extreme current limit ( see figure 5 ) (7) i lim_sw i lim_sw_ex -2.25 -3.75 -3.5 -4.5 -4.25 -6.00 a sw drain source on resistance (7) i d = 500 ma, v bat = 5.0 v r ds(on) ? ? 200 m thermal shutdown junction temperature (7) ts h ts l ? 155 ? ? 195 ? c thermal shutdown hysteresis (7) ts hys 1.0 ? 20 c vdd3 linear regulator v dd3 output voltage (includes line and load regulation) i vdd3 = 0 to -500 ma, see table 2 for v dd3 output settings v dd3 -3.0 ? 3.0 % v dd3 dropout voltage (v ddh - v dd3 ) i vdd3 = -800 ma (vdd3 set to 3.3 v via p1, p2, p3 and with an external transistor) v dd3_do ? 1.1 1.5 v v dd3_b current limit, v dd3_b = 0 v, ka_v bat = 14 v, v bat = 14 v ka_v bat = 5.0 v, v bat = 5.0 v i vdd3b_lim -20 -20 ? ? -50 -50 ma notes 7. guaranteed by design.
analog integrated circuit device data freescale semiconductor 9 33730 electrical characteristics static electrical characteristics vdd3 standby linear regulator v dd3 standby output voltage (includes line and load regulation) i vdd3_sby = 0 to -15 ma, see table 2 for vdd3_sby output setting v dd3_sby -15 ? 15 % v dd3 dropout voltage (ka_v bat - v dd3 ) standby mode (vdd3 set at 3.3 v via p1, p2, p3) i vdd3 = - 10 ma v dd3_do ? ? 1.4 v v dd3 standby current limit, v dd3 = 0 v ka_v bat = 14 v, v bat = 14 v ka_v bat = 5.0 v, v bat = 5.0 v i vdd3sby_lim -20 -20 ? ? -50 -50 ma thermal shutdown junction temperature (8) ts h ts l ? 150 ? ? 190 ? c thermal shutdown hysteresis (8) ts hys 5.0 ? 20 c vddl linear regulator v ddl output voltage (includes line and load regulation) i vddl = 0 to -500 ma, see table 1 for v ddl output setting v ddl -3.0 ? 3.0 % v ddl_b dropout voltage (v ddh - v ddl ) (vddl set at 3.3 v via p1, p2, p3) i vddl = -800 ma v ddl_do ? ? 280 mv v ddl_b current limit, v ddl = 0 v ka_v bat = 14 v, v bat = 14 v ka_v bat = 5.0 v, v bat = 5.0 v i vddl_lim -18 -18 ? ? -50 -50 ma vkam standby linear regulator v kam output voltage (includes line and load regulation) i vkam = 0 to -15 ma, see table 1 for v kam output setting v kam -15 ? 15 % v kam dropout voltage (ka_v bat - v kam ) i vkam = -10 ma, v kam set to 5.0 v (p1 = l, p2 = h, p3 = l) v kam_do ? ? 1.4 v vkam standby linear regulator (continued) v kam current limit, v kam = 0 v ka_v bat = 14 v, v bat = 14 v ka_v bat = 5.0 v, v bat = 5.0 v i vkam_lim -20 -20 ? ? -50 -50 ma thermal shutdown junction temperature (8) ts h ts l ? 150 ? ? 190 ? c thermal shutdown hysteresis (8) ts hys 5.0 ? 20 c notes 8. guaranteed by design. table 5. static electrical characteristic(continued) characteristics noted under conditions 6.0 v ka_v bat = v bat 26.5 v, - 40 c t a 125 c using the typical application circuit, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33730 electrical characteristics static electrical characteristics sensor supplies vref1, vref2 v ref on-resistance, i vref = -100 ma r ds(on) ? ? 500 m v ref current limit, v ref = -1.0 v (9) i ref_lim -150 -280 -450 ma v ref reverse current limit, v ref = 26.5 v (9) i ref_revlim ? ? 40 ma v ref leakage current, v ref shut down, v ref = -1.0 v (9) i ref_revlim -2.0 ? ? ma thermal shutdown junction temperature (10) ts h ts l ? 150 ? ? 190 ? c thermal shutdown hysteresis (10) ts hys 5.0 ? 20 c supervisory and control circuits v ign input voltage threshold v bat = 14.0 v, ka_v bat = 14 v v ign_ih v ign_il 4.0 2.0 4.3 2.15 4.6 2.4 v v ign hysteresis v ign-hys 1.7 ? ? v v ign pull-down current @ 5.0 v v bat = 14.0 v, ka_v bat = 14 v i pd 10 30 60 a regon input voltage threshold v bat = 14.0v, battery voltage = 14v v ih v il 1.7 -0.3 ? ? ? 1.0 v regon input voltage threshold hysteresis v ihys 0.1 0.3 0.4 v regon pull-down current @ 3.0 v i pd 5.0 ? 30 a programming pin input voltage threshold v bat = ka_v bat = 14 v v ih v il 2.5 -0.3 ? ? v bat 1.0 v programming p1, p2, p3 leakage current @ 14.0 v i pd ? 1.0 5.0 a v ddh reset upper threshold voltage ( v ddh /v ddh ) 4.0 8.0 13.0 % v ddh reset lower threshold voltage ( v ddh /v ddh ) -3.0 -8.0 -13.0 % v ddl reset lower threshold voltage ( v ddl /v ddl ) -3.0 -8.0 -13.0 % v dd3 reset lower threshold voltage ( v dd3 /v dd3 ) -3.0 -8.0 -13.0 % v dd3_sby reset lower threshold voltage ( v dd3_sby /v dd3_sby ) -3.0 -12.5 -30 % v kam reset lower threshold voltage ( v kam /v kam ) -3.0 -12.5 -30 % rsth , rstl , rst3 , rstkam low-level output voltage i ol = 5.0 ma ? ? 0.4 v ign_on low-level output voltage i ol = 5.0 ma ? ? 0.4 v notes 9. the short circuit transient events on the vref outputs must be limited to the voltage levels specified in the maximum ratings and slew rates of less than 2.0 v/s, otherwise damage to the part may occur. refer to the paragraph sensor supplies (vref1, vref2) on page 18 and typical application circuit diagrams on figure 8 ,and figure 9 for recommended vref output termination. 10. guaranteed by design. table 5. static electrical characteristic(continued) characteristics noted under conditions 6.0 v ka_v bat = v bat 26.5 v, - 40 c t a 125 c using the typical application circuit, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33730 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 6. dynamic electri cal characteristics characteristics noted under conditions 6.0 v ka_v bat = v bat 26.5 v, - 40 c t a 125 c using the typical application circuit, unless otherwise noted. characteristic symbol min typ max unit general power on reset delay time (hr timer) (see table 8 ) (time to reset up after regulator in regulation) t d_por 0 ? 68 ms power on reset delay time (hr timer) accuracy (33 k resistor) 8.0 ? 12 ms programming pin latching delay (11) t ld_p ? 500 ? s switching regulator oscillator frequency (switching freq.) range - adjustable ( figure 4 ) freq 100 ? 500 khz oscillator frequency tolerance at 100 khz (freq pin open) f tol 90 ? 110 khz sw node rise time, v bat = ka_v bat = 14 v, i sw = 500 ma (11) sr pin shorted to sw pin sr pin open sr pin shorted to boot pin t sw_r ? ? ? 0.96 1.82 2.38 ? ? ? v/ns sw node fall time, v bat = ka_v bat = 14 v, i sw = 500 ma (11) sr pin shorted to sw pin sr pin open sr pin shorted to boot pin t sw_f ? ? ? 0.83 0.83 0.83 ? ? ? v/ns notes 11. guaranteed by design.
analog integrated circuit device data 12 freescale semiconductor 33730 functional description introduction functional description introduction the 33730 multi-output power supply integrated circuit addresses the system power supply needs for applications using the freescale 32-bit microc ontroller family architecture. functional pin description hardware reset timer (hrt) this pin is the hardware reset timer input, which provides delays for the reset outputs. this delay is programmed by an external resistor to gnd. vkam reset ( rstkam ) this pin is an open drain reset output monitoring the v kam supply to the microprocessor. th is output is actively pulled low when the vkam output voltage falls below its reset threshold level. vddh reset ( rsth ) this pin is an open drain reset output monitoring the vddh regulator. this output is actively pulled low when the vddh output voltage falls below its reset lower threshold level or when the vddh output voltage exceeds its reset upper threshold level vddl reset ( rstl ) this pin is an open drain reset output monitoring the vddl regulator. this output is acti vely pulled low when the vddl output voltage falls below its reset threshold level. vdd3 reset ( rst3 ) this pin is an open drain reset output monitoring the vdd3 regulator. this output is acti vely pulled low when the vdd3 output voltage falls below its reset threshold level. vref output 2 (vref2) this pin is output of the protected supply vref2. this output supplies sensors outside of the electronic control module and therefore it is prot ected against a battery short and short to -1.0 v. this pin is supplied from the v ddh through the internal protection fet. vddl regulator (vddl) this pin is the v ddl regulator output feedback pin. the emitter of vddl regulator external npn pass transistor is connected to this pin. vddh regulator (vddh) this pin is the 5.0 v output feedback pin of the buck regulator. this pin is also a power input for the protected outputs vref1 and vref2. vddl regulator base drive (vddl_b) vddl linear regulator base drive. this output supplies current into the base of the regulator external pass npn transistor. vref output 1 (vref1) this pin is output of the pr otected supply vref1. this output supplies sensors outside of the electronic control module and therefore it is protected against short battery and short to -1.0 v. this pin is supplied from the v ddh through the internal protection fet. regulator hold on (regon) regulator hold on input control pin. the 33730 can be enabled or kept in the normal operational mode by holding this pin high. this is a 5.0 v logic input. vign status ( ign_on ) this open drain output signals th e status of the vign pin. this logic output is actively pulled low when the vign control input is pulled high. compensation (vcomp) this pin provides switchin g pre-regulator compensation network. it is the output of the switching regulator error amplifier. inverting input (inv) this pin is the inverting input of the switching regulator error amplifier. frequency adjustment (freq) this is the frequency adjustment input of the switching regulator. the operating frequency of the switching regulator can be programmed by an external resistor from this pin to ground. programming pin 1 (p1) programming pin 1 for the vdd3, vddl, and vkam reference voltage. the output voltage of the vdd3, vddl and vkam regulators can be programmed by the p1, p2, and p3 pins (see table 7 ).
analog integrated circuit device data freescale semiconductor 13 33730 functional description functional pin description programming pin 2 (p2) programming pin 2 for the vdd3, vddl, and vkam reference voltage. the output voltage of the vdd3, vddl and vkam regulators can be programmed by the p1, p2, and p3 pins (see table 7 ). programming pin 3 (p3) programming pin 3 for the vdd3, vddl, and vkam reference voltages. the output voltage of the vdd3, vddl and vkam regulators can be programmed by the p1, p2, and p3 pins (see table 7 ). protection fet drive (pfd) reverse battery protection fet gate drive. this pin is an output drive for the gate of the external reverse battery protection n-channel fet. bootstrap (boot) this pin is connected to the bootstrap capacitor. it provides the supply power for the switching regulator high- side drive. slew-rate (sr) slew-rate control of the switching regulator. the slew-rate of the switching regulator can be adjusted by connecting this pin to switch node (sw pin, slow slew-rate selection), boot pin (fast slew-rate selection), or it can be left open (medium slew-rate selection). switch node (sw) this pin is the source of th e switching regulator internal power switch (n-channel mosfet source). battery voltage supply (vbat) voltage supply to the ic (external reverse battery protection is recommended). keep alive supply (ka_vbat) this pin is the keep alive supply input. this input is reverse battery protected. this input supplies power to the internal supply and bias circuits that have to do with this vkam and other always-on supplies. charge pump (cp) external reservoir capacitor of the internal charge pump. this charge pump provides the voltage needed to sufficiently enhance the gates of the inter nal n-channel mosfets (vref1, vref2, and vddh) during the low battery condition. keep alive memory (vkam) keep alive memory (standby) supply output. this output supplies power for the module keep-alive memory. this output is always on, if the voltage at the ka_vbat pin is above 4.5 v. vdd3 linear regulator (vdd3) this is a vdd3 regulator output feedback pin.the emitter of vdd3 regulator external npn pass transitory is connected to this pin. this pin can programmed to be the output of the vdd3 standby regulator (see table 7 ). vdd3 linear regulator base drive (vdd3_b) this pin can be used also as an additional standby regulator without the external pass transistor.this output supplies current into the base of the regulator external pass npn transistor. ground (gnd) this pin is the ground pin of the integrated circuit. voltage ignition (vign) this pin is the turn-on cont rol input that is controlled through an ignition switch. this pin is reverse battery protected.
analog integrated circuit device data 14 freescale semiconductor 33730 functional description functional internal block description functional internal block description 5.0 volt buck regulator this is the main regulator t hat supplies 5.0 volts to the following protected and regulat ed outputs, vref1, vref2, vdd3, and vddl. oscillator this is the frequency source for the switching (buck) 5 volt regulator. the frequency of oscillation is selected by an external resistor to ground. band gap reference this is the main voltage reference, which is used as the standard for all the current and voltage sources in the mc33730. protection fet driver the protection fet is used to prevent reverse battery connections from damaging the mc33730. the gate drive for the protection fet is provided by this driver circuit. sleep/wake circuitry this circuitry is responsible for the two main modes of operation for the mc33730, sleep mode and wake mode. in the sleep mode, only the keep alive outputs are active, and the rest of the circuitry is in a low power drawing sleep state. in the wake mode, the mc33730 is fully functional and normal current is being consumed. ignition driver this block of circuitry controls all the voltage outputs, except for the keep alive voltage output(s). it also provides an output signal to indicate that the ignition switch has been activated. vref1 this output is one of two protec ted 5.0 volt outputs that can be used to supply external sensors or other analog circuits requiring a regulated, short-ci rcuit protected 5.0 volt supply. vref2 this output is one of two protec ted 5.0 volt outputs that can be used to supply external sensors or other analog circuits requiring a regulated, short-ci rcuit protected 5.0 volt supply. vdd3 regulator this is one of three, voltage programmable, regulated supplies. this supply is contro lled by the ignition switch. vddl regulator this is one of three, voltage programmable, regulated supplies. this supply is contro lled by the ignition switch. vkam this is one of three, voltage programmable, regulated supplies. this supply is not controlled by the ignition switch. voltage programming p1, p2, and p3 are three logic level inputs that control the voltage that is available on the vdd3, vddl and vkam outputs. table 7 indicates the 8 different combinations of p1, p2, and p3 and the resultant voltage values. band gap reference sleep/wake circuitry voltage programmming input protection fet driver ignition input oscillator 5 volt buck switching regulator 5 volt protected outputs (vref1, vref2) linear regulator outputs (vddl, vdd3, vkam) ignition driver reset circuitry input functions internal functions output functions mc33730 - functional block diagram
analog integrated circuit device data freescale semiconductor 15 33730 functional description functional internal block description reset circuitry there are four open drain reset lines that indicate the status of the four voltage outputs; vddh, vddl, vdd3, and vkam. they are labeled: rsth, rstl, rst3, and rstkam. regon input this input is or?d with vign. ho wever, it is a 5.0 volt logic input, as opposed to vign, which is a v bat level input. this input is controlled by an mcu i/o pin, to hold power up when the ignition switch is turned off, so housekeeping functions can be performed before power is shut off, by lowering the regon line. if regon is not needed, it should be tied to gnd.
analog integrated circuit device data 16 freescale semiconductor 33730 functional device operation operation description functional device operation operation description introduction the 33730 has two supp ly inputs. the ka_vbat pin is the supply input for the standby regulators v kam (and optionally v dd3_sby, see table 7 ) and for the internal supply circuits. the vbat pin is the power input of the integrated buck regulator, which steps-down t he protected battery voltage providing directly the 5.0 v system supply v ddh . v ddh provides power for the main linear regulator(s) v ddl , v dd3 , and also for the other module circuits requiring 5.0 v supply voltage (e.g. protected v ref1,2 outputs). if the supply voltage ramps fr om zero volts up to its nominal level, the 33730 will st art at the latest when the supply (battery) voltage reaches v stup at the ka_v bat pin. if the supply voltage ramps down, the 33730 will keep operating (with degradation of th e output voltage regulation) down to v uvlo_f at the ka_vbat pin. the v kam output stays operational down to v uvlo_f at the ka_vbat pin. the 33730 will operate in systems with and without standby mode. in the standby (sleep) mode of operation the ic will draw maximum i q quiescent current, assuming only the vkam is used as a standby output, and it is unloaded. when v dd3 is used as an additi onal standby output the quiescent current increases by approximately another 100 a. power up the 33730 will safely power up when the power is applied simultaneously (hot plugged) or in the random sequence to the ka_vbat, vbat and vi gn (or regon) inputs. power down the 33730 will safely power down when the power is disconnected from any of the ka_vbat, vbat inputs or when control signals the vign or regon inputs go low. undervoltage lo ck-out (uvlo) there is an under-voltage lock-out feature implemented into the ic. when th e battery voltage at the ka_vbat pin falls below v uvlo_f the under-voltage comparator initiates the power down sequence for the whole ic. the under-voltage lock-out circuit has a v uvlo_hys hysteresis and 5.0 s glitch filter in order to prevent spurio us tripping its threshold level and consequent system oscillations between the on and off states. switching regulator the 33730 switching regulator is a fixed frequency (externally adjustable) pwm voltage mode controller with integrated low-r ds(on) n-channel power mosfet. this architecture is widely flexible and provides a possibility to optimize its operation over a wide range of input voltages. the 33730 switching regulator pr ovide the following features: adjustable switching frequency the adjustable frequency feature provides the ability to modify the switcher performance for optimized cost (higher frequency, smaller, cheaper components), or higher efficiency and better emc performance (lower switching frequency for reduced losses and emi). the operating frequency of the switching regulator can be adjusted by means of an external resistor r f connected from the freq pin to ground (see figure 4 ). figure 4. switching regulator frequency vs. r freq value adjustable slew-rate the adjustable slew-rate option allows, with selection of the right switching frequency, optimization of the system for emc performance. over-voltage lock -out (shutdown) the over-voltage lock-out (s hutdown) feature turns the switching regulator off when the input voltage exceeds the v shdn_r limit. this extends the 33730 capability to survive the severe load dump conditions up to max v bat . operation at 100% duty cycle the internal charge pump is used to enhance the power mosfet gate when the switching regulator reaches 100% duty cycle during the low battery conditions. the switching regulator output voltage v ddh is regulated to provide 5.0 v @ 2.0 a with 2% accuracy and it is intended frequency vs r freq 0 100 200 300 400 500 600 0 2040 6080100 r freq [kohm] switching frequency [khz] f sw ? 18.48 + (5098.7/r freq ) f sw i s the switch frequency in khz r freq is the resistor value in kohms
analog integrated circuit device data freescale semiconductor 17 33730 functional device operation operation description to directly power the digital and analog circuits of the electronic control module (ecm). the switching regulator output current is also used by the following linear regulators v dd3_3 , v ddl , and sensor supplies v ref1 , and v ref2 . the direct voltage conversion to v ddh = 5.0 v together with the protection fet driver ci rcuit allows operation of the ic at very low battery voltages, which would otherwise require to use a boost regula tor (with an additional system cost) or a different and more expensive switching converter topology (e.g. flyback). short circuit protection the switching regulator is protected against the over- current and short-circuit conditions. it integrates a current limit circuit, which has two threshold levels - the pulse by pulse, and the extreme. pulse by pulse current limit pulse-by-pulse current limit threshold has a nominal value set i lim_sw . when the current flowing through switching regulator power fet exceeds this value the power fet is immediately turned off. during the next switching cycle the power fet is turned on again until it is commanded off by its natural duty cycle or until the current reaches the threshold level again. it should be noted that the current limit is blanked for several tens of nanoseconds during the turn-on and turn- off transition times in order to prevent erroneous turn off due to the current spikes caused by switcher parasitic components. extreme current limit. in some cases, during the ov er-current or short-circuit condition, the inductor current does not sufficiently decay during the off time of the swit ching period. the current rise during the current limit blanking time is higher than the decay during the off time. in this case the current in the inductor builds up every consecutive sw itching cycle. in order to prevent the power fet failure during this condition an extreme current limit has been implemented. when the current flowing through the power fet reaches the i lim_sw_ext threshold, the switching regulator will shut off for 500 s, before the switch ing regulator is allowed to turn on again (see figure 5 ). figure 5. 33730 current limit soft start the switching regulator has an integrated soft-start feature. during the soft-star t sequence the duty cycle of the internal power switch will be gradually increased from low value to the regulation level. this technique prevents any undesirable inrush current into the buck regulator output capacitor. linear regulators the 33730 integrates two linear regulator control circuits v dd3 (programmable), v ddl (programmable) both capable of driving up to 15 ma (min.) base current into the external pass npn transistors. the output volt age of both linear regulators is monitored at their feedback pins (v dd3 and v ddl ). if the voltage at any of the v dd3 , v ddl feedback pins fall below their regulation level, the supervisory reset control circuits will assert the corresponding reset signal ( rstl , and/or rst3 lines will be pulled low). see table 7 for the output voltage selection details. the linear regulators will stay in regulation down to 4.5 v at the ka_vbat pin. the 33730 linear regulators offer high flexibility and variability of the module design in terms of selectable output voltages as well as wide ran ge of output current capability. there several types of suitable external pass npn transistors which could be used. the choice of the particular type depends mostly on the expected power dissipation of the pass transistor. the following parts provide good solution and have been bench tested with the 33730: bcp68t1 (sot-223) njd2873t4 (dpak) mjb44h11 (d 2 pak) available from on semiconductor. note: the 33730 linear regulators have been designed to use low esr ceramic output capacitors - see figure 8 and figure 9 for the recommended values. standby regulators the 33730 integrates two standby linear regulators, the v kam and the optional standby regulator v dd3 (see figure 9 ) for the optional standby circuit).the output voltage levels of both standby linear regulators are programmable and supervised by the reset control circuits ( rstkam , and/or rst3 ). both the v kam and v dd3 outputs are capable of delivering i vkam_lim and i vdd3_lim of load current. see table 7 for the v kam and v dd3 standby output voltage selection details. the v kam standby regulator will keep functioning even below v uvlo_f but the specified drop out voltage may not be maintained. note: the 33730 standby regulators have been designed to use low esr ceramic output capacitors - see figure 8 and figure 9 for recommended values. t blank t sw i lim 3.5a 4.5 a 500us d elay t sw 0 inductor cu rrent switcher fet gate ex t . i lim
analog integrated circuit device data 18 freescale semiconductor 33730 functional device operation operation description programming linear regulator output voltage the output voltage of the vdd3, vddl and vkam outputs can be externally programmed by placing logic levels on the programming pins p1, p2, and p3 (see table 7 ). this extends the application flexibilit y of the ic without having to use an external resistor divider, thus improving the regulator accuracy over the whole temperature range, and reducing the component count. the logic level of the programming pin (px) can be selected by tying the pin to ground (logic level "0") or to protected battery voltage (logic level "1"). programming pins must never be left floating, they must be tied to either ground or protected battery voltage. the programming information is read and latched with the 500 s delay after the power is applied to the ic. low battery operation when the battery voltage falls below the specified minimum value, the 33730 switching regulator will enter a 100% duty cycle mode of o peration and its output voltage v ddh will follow the decreasing battery voltage. if the battery voltage continues to fall, the v ddh voltage reaches its reset threshold level, and the rsth signal will be pulled low, but the other linear regulators will continue to operate, and their monitoring signals stay high as long as the vddh provides sufficient headroom for the regulators to stay in their regulation limits (see figure 6 and figure 7 ). if the battery voltage continues to fall, the linear regulators would not have sufficient headroom to stay in regulation, and their resets would be asserted ( rstl , rst3, or both would be pulled low). at that moment the power down sequence would be engaged. the v kam standby regulator will operate down to (v kam and v kam_do) and v kam-do at the ka_vbat pin. power sequencing (vddh, vdd3, vddl) v ddh , v dd3 , and v ddl are power sequenced by means of internal pull-down fets. during the power up sequence, v dd3 and v ddl will follow v ddh . during the power down sequence the v dd3 and v ddl outputs will be pulled down by the internal pull-down power fets, and v ddh will be shut off with a defined delay (~100 s typ.). in order to engage the power down sequence, the following conditions have to be met: ( vign . regon ) + uvlo = power down the vdd3 output is not power sequenced when used as a standby regulator. sensor supplies (vref1, vref2) there are two sensor supplies, vref1 and vref2, integrated into the ic. they are internally connected to v ddh through power mosfets which protect against short to battery and short to ground conditions. severe fault conditions on the vref1 and vref2 outputs, like shorts to either ground or battery, will not disrupt the operation of the main regulator v ddh , or cause assertion of any reset signal. important note: the vref outputs must be externally protected against transient voltage events with slew rates faster than 2.0 v/ s, otherwise damage to the part may occur. a practical and inexpensive solution consists of using a series rc network connected from the vref output to ground (see figures 8 and 9 for typical component values). other means, such as a single electrolytic capacitor with its capacitance value c > 10 f, may be also used. protection fet drive (pfd) the protection fet drive circuit allows using an optional n-channel protection mosfet (instead of a standard reverse protection diode) to pr otect against a reverse battery voltage condition. this appr oach improves the operating capabilities at very low battery voltages. an internal charge pump is used to enhance the protection fet gate during nominal and low battery conditions. the charge pump will be enabled at the startup voltage. when the battery voltag e gets sufficiently high, the protection fet is turned off and the integrated circuit power input (v bat pins) are supplied through the body diode of the protection fet. use of the protection fet is not necessary in systems already using a protection diode, relay or when no reverse battery protection is required. control input (vign) the vign pin is used as a control input to the ic. the regulation circuits will function and draw current from v bat when v ign is high (active) or when the regon pin is high. the vign pin has a v ihn-ih power-up threshold v ign-il typical power-down threshold) and v ign-hys (minimum) of hysteresis. v ign is designed to operate up to max v bat battery while providing reverse battery and max v bat load dump protection. table 7. programming vdd3 , vddl, vkam output voltage p1 p2 p3 v dd3 v ddl v kam high high high 3.3 v 2.6 v 2.6 v high high low 3.3 v 3.3 v 3.3 v high low high 3.3 v 1.5 v 1.0 v high low low 3.3 v 3.3 v 1.0 v low high high 3.3 v standby 3.3 v 1.0 v low high low 2.0 v 3.15 v 5.0 v low low high 2.6 v standby 3.3 v 1.0 v low low low 2.6 v standby 3.3 v 1.5 v the programming pins can be tied high, to protected battery voltage, or low, to ground.
analog integrated circuit device data freescale semiconductor 19 33730 functional device operation operation description regon the regon feature permits the microcontroller to select a delayed shutdown of the 33730. it holds off the activation of the reset signals to the microcontroller after the v ign signal has transitioned. this allows th e microcontroller to control the power up and power down of the main regulator outputs except for the standby supp lies. the regon pin input threshold voltages allow control by the standard 2.5 v (up to 5.0 v) logic ics. hardware resets ( rstl , rst3 , rsth , and rstkam) the hardware resets are open drain, active low outputs capable of sinking 5.0 ma current and able to withstand +7.0 v. the rstl control circuit monitors the v ddl output. if the v ddl output is out of regulation (low), the device will assert the rstl signal low. the rst3 control circuit monitors the v dd3 output. if the v dd3 output is out of regulation (low), the device will assert the rst3 signal low. the rsth control circuit monitors the v ddh output. if the v ddh output is out of regulation (low or high), the device will assert the rsth signal low. the rstkam control circuit monitors the v kam output. if the v kam output is out of regulation (low), the device will assert the rsth signal low. all reset monitoring circuits have a 20 s delay filter to avoid unintended resets caused by noise glitches on the regulator output lines. hr timer the hr (hardware reset) timer provides the delay between the time when the partic ular regulator output voltage is in regulation and the release of the reset signal. this delay can be programmed by a single external resistor. this solution provides better accuracy than the commonly used external rc timer. the hr timer delay can be programmed in eight 8ms steps from 0 to 56 ms (see table 8 ) . figure 6. battery voltage ramp up table 8. hr timer delay programming programming resistor value r hrt [ohms] delay (typ.) [ms] 68 k 0 33 k 10 16 k 19 8.2 k 29 3.9 k 39 2.0 k 48 1.0 k 58 470 68 v kam =1.0v battery vo ltage rs t ka m por delay rst l, rst 3 por delay 4.5v rsth por dela y v dd l =v dd3 =3.3v v ddh =5.0 v
analog integrated circuit device data 20 freescale semiconductor 33730 functional device operation operational modes figure 7. battery voltage ramp down operational modes the 33730 can operate in the two modes: low quiescent current sleep mode and normal mode of operation. sleep mode the 33730 operates in the sleep mode when both the vign pin and the regon pins are pulled low. both of these pins have internal pull-downs, which assures that the ic is in this defined state when those pins are left open. when the ic enters the sleep mode, all major functions are disabled except for the standby regulators. the keep- alive regulator vkam stays always operational (see table 7 ). if this output stays unloaded, the ic in the sleep mode consumes very low quiescent current (i q ). if the vdd3 output was programmed as a vdd3 standby regulator (see table 7 ), it too stays operational during the sleep mode, as well as the vkam regulator. in this case, the ic consumes about 100 a of additional quiescent current (assuming both vkam and vdd3 standby outputs are unloaded). note: in the sleep mode, the rstkam and rst3 are not active and their outputs (a s well as the outputs of rstl and rsth ) are in the high-impedance state. normal mode the 33730 enters the normal mode of operation when either the vign pin or the regon pin is pulled high. in this case the ic is fully operationa l with all regulator outputs ready to supply power and all control, monitoring and protection features activated. v ka m =1.0v 3.0v battery vo lta ge rs t ka m rs t l, rs t 3 rsth v ddl =v dd 3 =3.3v v ddh =5.0v 10 0u s vdd3, vddl ou t o f regulation vddh tu rn ed off vdd3, vddl actively pulled low vddh ou t o f re gu l ati o n 4.5v
analog integrated circuit device data freescale semiconductor 21 33730 typical applications operational modes typical applications figure 8. 33730 typical application circuit table 9. programming output voltage (bold denotes selected combinations) p1 p2 p3 v dd3 v ddl v kam high high high 3.3 v 2.6 v 2.6 v high high low 3.3 v 3.3 v 3.3 v high low high 3.3 v 1.5 v 1.0 v high low low 3.3 v 3.3 v 1.0 v low high high 3.3 v standby 3.3 v 1.0 v low high low 2.0 v 3.15 v 5.0 v low low high 2.6 v standby 3.3 v 1.0 v low low low 2.6 v standby 3.3 v 1.5 v standby control vk am 15 ma,i li m , t li m feed forward ramp gen era tor bu ck con tr ol l ogi c oscillator hs drive, le vel sh if ter b oot sw v bg sr inv vcomp vddh vref1 hrt ka _v bat vb at vkam rs t h rstkam gnd ba nd -g ap refe r ence v bg hr timer vddl i li m vref2 freq vddl_b v ddh reset detect vdd3_b vdd3 vbat sw 5. 0 v, i li m =1 50 ma 26 .5v,- 1 v,t lim t-lim ref . volt age prog rammin g block pr ot ecti o n fe t drive pfd uvlo /ovlo v ddh =5.0v @ 2000ma total battery p1 p2 v ka m ,v ddl ,v dd3 , v dd3_sby ref. voltage charge pu mp 5.0 v, i lim =150 ma 2 6. 5v,-1v,t li m vdd3 i lim ,t li m cp cp rstl vddl p3 o pti o n al pr o tect io n fe t v dd3 reset detect rst3 v kam reset detect v dd l rese t det ect vign re gon ign_on en ab le 22uh ss 26 10 0u f 20k 5. 0k 430r 1. 5n f 5 6pf 20k 2.2nf 10 nf 1 0 0nf 1.0 uf 4. 7uf 4. 7uf 10uf 5.1k 4x 3.3 uh 10 0u f 1.0uf 1. 0uf 10nf 5. 1k 10nf 10 nf feed ba ck comp ens ati on ne two rk 10 nf cp q1 q2 vdd3_sby i lim ,t li m 10 nf 1.5 v 3.3 v 5.0 v 5.0 v 1. 0 v 1. 5r 1. 0uf 1.5r r hrt r fr e q notes 12. the v ddh total current includes the sum of all output currents of the ic. 13. higher resistance (60 k) and high er capacitance (4.7nf) in the com pensation network will reduce the v ddh overshoot. compensation network values should be optimized for specific circuit applications. recommended q1, q2: bcp68t1 (sot-223) njd2873t4 (dpak) mjb44h11 (d2pak) v ddh = 5.0 v @ 2000 ma (11) 10.4 k 1.98 k 20-60 k (12) 2.2-4.7 nf (12)
analog integrated circuit device data 22 freescale semiconductor 33730 typical applications operational modes figure 9. 33730 typical application, vdd3 standby output @ 15 ma table 10. programming output voltage (b old denotes selected combinations)' p1 p2 p3 v dd3 v ddl v kam high high high 3.3v 2.6v 2.6v high high low 3.3v 3.3v 3.3v high low high 3.3v 1.5v 1.0v high low low 3.3v 3.3v 1.0v low high high 3.3 v standby 3.3 v 1.0 v low high low 2.0 v 3.15 v 5.0 v low low high 2.6 v standby 3.3 v 1.0 v low low low 2.6 v standby 3.3 v 1.5 v standby control vk am 15 ma,i lim , t lim feed forward ramp gen era tor bu ck control logic oscillator hs drive, le vel sh if ter boot sw v bg sr inv vcomp vddh vref1 hrt ka _v bat vb at vkam rs t h rstkam gnd ba nd -g ap reference v bg hr timer vddl i lim vref2 freq vddl_ b v ddh reset detect vdd3_ b vdd3 vbat sw 5. 0 v, i lim =1 50 m a 26 .5v,-1 v,t lim t-lim ref. voltage prog rammin g block prot ectio n fe t drive pfd uvlo /ov lo v ddh =5.0v @ 2000ma total ba tte ry p1 p2 v ka m ,v ddl ,v dd3 , v dd3_sby ref. voltage charge pu mp 5.0 v, i lim =150 ma 2 6. 5v,-1v,t lim vdd3 i lim ,t lim cp cp rstl vddl p3 op t i o nal pro tect io n fe t v dd3 reset detect rst3 v kam reset detect v dd l rese t det ect vign re gon ign_on en ab le 22uh ss 26 10 0u f 20k 5. 0k 430r 1. 5n f 56pf 20k 2.2nf 10 nf 1 0 0nf 1.0 uf 4. 7uf 4. 7uf 10uf 5.1k 4x 3.3 uh 10 0u f 1.0uf 1. 0uf 10nf 5. 1k 10nf 10 nf feed ba ck comp ens ation ne two rk 10 nf cp q1 vdd3_sby i lim ,t lim 10 nf 1.5 v 3. 3 v sta nd b y 5.0 v 5.0 v 1. 0 v 1. 5r 1. 0uf 1.5r r hrt r fr e q notes 14. the v ddh total current includes the sum of all output currents of the ic. 15. higher resistance (60 k) and higher capacitance (4. 7nf) in the compensation network will reduce the v ddh overshoot. compensation network values should be optimized for specific circuit applications. recommended q1, q2: bcp68t1 (sot-223) njd2873t4 (dpak) mjb44h11 (d2pak) v ddh = 5.0 v @ 2000 ma (13) 10.4 k 1.98 k 20-60 k (14) 2.2-4.7 nf (14)
analog integrated circuit device data freescale semiconductor 23 33730 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98arl10543d listed below. dimensions shown are prov ided for reference only. ek suffix (pb-free) 32-pin soicw - ep 98arl10543d revision c
analog integrated circuit device data 24 freescale semiconductor 33730 packaging package dimensions (continued) package dimensions (continued) ek suffix (pb-free) 32-pin soicw - ep 98arl10543d revision c
analog integrated circuit device data freescale semiconductor 25 33730 packaging package dimensions (continued) package dimensions (continued) ek suffix (pb-free) 32-pin soicw - ep 98arl10543d revision c
analog integrated circuit device data 26 freescale semiconductor 33730 reference section package dimensions (continued) reference section table 11. reference documents reference description mc33730er mc33730, mask da03m89h, rev. 4.2 errata
analog integrated circuit device data freescale semiconductor 27 33730 revision history revision history revision date description of changes 5.0 2/2009 ? initial release 6.0 2/2010 ? updated resistors on the inv pin (page 2, 20, 21) ? clarified regon pin operation (page 3, 9, 11, 14) ? added sensor supply max. slew rate (page 5,17) ? clarified por delay section with updated typical values (page 10,18) ? modified the sw rise and fall time to v/ns (page 10) ? provided a switching frequency equation (page 15) ? updated the recommended compensation network values (page 20,21) ? made format layout corrections 7.0 4/2010 ? corrected typographical error on capacitor ( f to nf ) in figures 8 and 9. 8.0 8/2010 ? added note to page 4 (pin definitions) for pins p1, p2 and p3. ? revised paragraph in section; programming linear regulator output voltage on page 18 9.0 8/2012 ? added part number MC33730EK to the ordering information table ? added device variations on page 2 ? added reference section on page 26 ? updated freescale form and style
document number: mc33730 rev. 9.0 8/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or im plied copyright licenses granted hereunder to design or fabricate any integr ated circuits based on the information in this document. freescale reserves th e right to make changes without fu rther notice to a ny products herein. freescale makes no warranty, repr esentation, or guarantee regarding the suitability of its products for any particular purpo se, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically di sclaims any and all liability, including without limitation consequential or in cidental damages. ?typical? parameters that may be provided in freescale da ta sheets and/or specifications can and do vary in different applications, and actual performa nce may vary over time. all ope rating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its pate nt rights nor the rights of others. freescale sells products pursuant to sta ndard terms and conditions of sa le, which can be found at the following address: store.esellerate.net/store/ policy.aspx?selector=rt&s=str0326182960&pc. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, code test, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos, turbolink, vybrid, and xtrinsic ar e trademarks of freescale semiconductor, inc. all other product or service names ar e the property of their respective owners. ? 2012 freescale semiconductor, inc.

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